Lightly doped drain (LDD) regions have commonly been used to reduce the hot electron effect in a field effect transistor (FET). This is made possible by providing LDD regions which separate the source and drain regions from the channel region, thereby reducing the electric field at the source and drain pinch-off regions, and thus increasing the channel breakdown voltage and reducing electron impact ionization (hot electron effects).
An FET having LDD regions is typically fabricated in an active region of a substrate. The active region has a P-type background doping and is bounded by field oxide (FOX) regions which electrically isolate the FET from other devices formed in the same substrate. To form an N-channel FET, the conventional processing techniques implant regions located at both ends of a gate with a light dose of an N-type dopant using the gate as a mask. Two N regions formed by the implant define a channel underlying the gate. A spacer material layer is formed over the entire structure and etched so that spacers remain at the ends of the gate. These spacers overlie portions of the N.sup.- regions adjacent to the gate structures. Thereafter, a second implant is performed with a heavier dose of an N-type dopant to form N.sup.+ source and drain regions in the N.sup.- regions. During the second implant, the spacers mask the underlying N.sup.- regions. The N.sup.- regions which do not receive the second implant become the LDD regions. Thus, the width of the spacers defines the width of the LDD regions.
The conventional manner of forming spacers is to perform a blanket etch of a spacer material layer, typically an oxide layer, which is provided over the entire area of the substrate. However, because of non-uniformitics of the etching rate over the entire wafer area, there may be a removal of materials from the field oxide, referred to as oxide loss which undesirably reduces the threshold voltage of the FET.
One method of reducing oxide loss is to use an etch stop layer, for example, a silicon nitride (Si.sub.3 N.sub.4) layer, overlying the substrate, the gate, and the field oxide regions of a partially fabricated FET prior to forming the spacer material layer. The spacer material is formed of a material which can be selectively etched with respect to the etch stop layer. An etchant is selected which selectively etches the spacer material layer so that the nitride layer will not be penetrated by the etchant either during the etching of the spacer material layer to form the LDD spacers or during the etching to remove the LDD spacers. Such a method is described in U.S. Pat. No. 5,200,351 issued Apr. 6, 1993, to Zahra Hadjizadeh-Amini.
While the above method is able to reduce oxide loss, it involves four masking steps to form the source, drain and LDD regions in a typical Complementary Metal Oxide Silicon (CMOS) LDD fabrication process. The four masking steps are: an N.sup.- mask to form the N.sup.- regions, a P.sup.- mask to form the P.sup.- regions, an N.sup.+ mask to form N.sup.+ source and drain regions and a P.sup.+ mask to form the P.sup.+ source and drain regions. Each masking step typically includes the sequential steps of preparing the substrate, applying the photoresist material, soft-baking, aligning and selectively exposing the photoresist to radiation by using a mask, baking, hard baking, developing the patterns in the resist, hard baking, implanting a desired dose of a dopant with the required conductivity type, stripping the photoresist, and then cleaning of the substrate. These processing steps associated with each masking step adversely increase cycle time and process complexity and also introduce particles and defects, resulting in an increase in cost and yield loss. Hence, there is a need to provide a method for forming FET and CMOS transistors with LDD regions which reduces oxide loss, while at the same time lessens the number of masking steps required. The present invention addresses such a need.